1. Field of the Invention
This invention relates to the architecture of computer graphics display systems. More particularly this invention relates to a method and apparatus for interleaving pixel data transfer from a frame buffer to a memory display interface.
2. Art Background
In a typical computer graphics system, a video random access memory (VRAM) frame buffer stores pixel data for rendering images on a display device. A memory display interface may be employed to process the pixel data for the display device. The memory display interface processes the pixel data at programmable pixel rates and pixel depths, and implements special pixel functions. Pixel processing at programmable pixel rates enables support of display devices having differing characteristics (resolution, video timing, etc.), and support of VRAM frame buffers having differing access speeds. Processing of pixels having programmable pixel depths increases software compatibility.
The capacity of the frame buffer in existing systems can be increased by upgrading to higher density VRAM chips. The higher density VRAM chips require less space on a printed circuit board for a given frame buffer capacity. However, VRAM manufacturers have increased VRAM chip densities by increasing the number of bit planes in the VRAMs, rather than by increasing the depth of the VRAMs. For example, 256K by 4 bit VRAMs have evolved to 256K by 8 bit VRAMs to provide greater density. The 256K by 8 bit VRAMs reduce by one half the number of VRAM chips required for a given frame buffer capacity when compared with 256K by 4 bit VRAMs.
Unfortunately, the increased number of bit planes in the higher density VRAM chips requires an increase in the width of the video bus between the frame buffer and the memory display interface. For example, an existing system having eight 256K by 4 bit VRAMs may have a 32 bit video bus for transferring the pixel data from the frame buffer to the memory display interface. If the frame buffer capacity is doubled by upgrading to eight 256K by 8 bit VRAMs, the width of the video bus must increase to 64 bits to accommodate the increased number of bit planes. The increased width of the video bus requires a major redesign of the memory display interface, as well as major modifications to the printed circuit board layout. The major design modifications greatly increases the cost of upgrading existing systems.
As will be described, the present invention is a method and apparatus for interleaving pixel data transfer from a frame buffer to a memory display interface, which provides increased frame buffer capacity for existing memory display interface designs.